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    Basic Information

Technology developed: High Speed reconfigurable Power Electronic Controller (TP19767523871)
Category: Nil
Details of Inventor(s):
Inventor Institution/Organization/Company Department Designation
AJEESH A CDAC THIRUVANANTHAPURAM PEG SCIENTIST E
Technical Application Area: Energy/Power
If 'Other', please specify:
Please give more details of new technical application area:
Digital Controller for Power Electronics
Organization(s):
Centre for Development of Advanced Computing (CDAC) Pune
Affiliated Ministry: MeitY, Govt. of India
Type of technology development: Indigenous
Does the technology help in replacing any import items currently
procured from outside India?
Yes
Does the technology have export potential? Yes
Category of Technology developed: Futuristic
Stage of Development: Field Test
Please describe in detail including the TRL Level:
TRL LEVEL 6 DEPLOYED IN ACADEMIA LIKE IISC, NITs FOR LIBRARY DEVELOPMENT AND FAMILIARIZATION OF METHODOLOGY DEVELOPED

    Abstract:

Applications: Digital controller for AC drives ,Dc drives, Grid connected Applications, and other Power electronics Converters at a low cost and with reduced Obsolescence risk
Advantages: Conventional designs of Power Electronic control are based on microcontrollers and Digital signal Processors DSPs. Microcontrollers change too often and there is lots of re-work required to be done in order to keep pace with changing technology. We developed an FPGA based soft reconfigurable custom Power Electronic control processor with user defined Instructions design Methodology for Power Electronics applications. A reconfigurable architectures have proven to provide high performance in a wide range of applications. The user is designing a custom soft processor with his own instructions and CPU peripherals required for his application. This processor shall be downloaded to any FPGA then the FPGA becomes the physical processor. Depending on application the user shall change configurations or modules inside FPGA. As the algorithmic modules are in hardware the HSRPEC will perform faster than its software implementation in equivalent DSP implementation. Also, HSRPEC uses hardware parallel processing than software pipelining. As the processor design is in soft format which can be downloaded to any FPGA, processor obsolescence risk is minimum in HSRPEC methodology. The use of custom IPs reduces the software overhead, the number of lines in application program is less than its equivalent DSP and Microprocessor design. As we have the proven IP set and FPGA board which shall improve the time to market criteria. In HSRPEC at any point of time the user can shift from single core to multi core design without any change in FPGA board

    Technology Inputs:

Imported Equipment/Spare Parts:
Equipment/Spare Parts Year ITC-HS Code
FPGAs 2013-14
Indigenous Equipment/Spare Parts:
Equipment/Spare Parts Year ITC-HS Code
6 layer PCBs 2013-14
Power electronics Specific IPs designed in VHDL 2013-14
Imported Raw Materials:
Raw Materials Year ITC-HS Code
NA
Indigenous Raw Materials:
Raw Materials Year ITC-HS Code
NA
Existing R&D Facilities used:
Facilities Year ITC-HS Code
In house facility from CDAC Power Electronics Lab 2013-14

   Patents & Publications:

Patents:
Filed Patents (No.) Granted Patents (No.) Year
0 0 NA
Publications:
Submitted (No.) Published (No.) Year
0 1 2016-17

    Commercialization Potential:

Who are the Potential Licensees? Educational Institutes, We have transferred the technology to more than 10 premier academic Institutes All Power Electronics Converter Development Companies
What commercially available products address
the same problem?
Company Product Problem Addressed
Would you like to develop this invention further with
corporate research support?
Yes
Would you be interested in participating in cluster based
programs for commercialization research or business
planning for your invention?
Yes
      Submitted by: Rajasree S Date of Submission: 4-8-2020



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